1. Field of the Invention
The present invention relates to an electrode structure for a semiconductor chip, and more particularly to an electrode structure for a semiconductor chip forming a flip-chip connection for suppressing expansion of a crack.
2. Description of the Background Art
A conventional structure of an electrode pad for a flip-chip connection in a semiconductor device will be described with reference to the drawings. FIG. 11A is a diagram illustrating a typical flip-chip connection structure. In FIG. 11A, a semiconductor chip 1101 and an interposer substrate 1102 are connected to each other through solder bumps. FIG. 11B is a cross-sectional view of the flip-chip connection structure shown in FIG. 11A along lines A-A′ of FIG. 11A. In FIG. 11B, the semiconductor chip 1101 and the interposer substrate 1102 are connected to each other through the solder bumps 1103, and an underfill resin 1104 covers a connecting portion of the solder bumps 1103. Thus, a circuit formed inside the semiconductor chip 1101 is connected to the back surface of the interposer substrate 1102 through the solder bumps 1103, so that a mounting area is reduced, and a shortened wiring improves electric characteristics. Further, the connecting portion of the solder bumps 1103 is covered with the underfill resin 1104 so as to enhance the reliability of connections in the connecting portion of the solder bumps 1103.
The flip-chip connection pad formed inside the semiconductor chip 1101 may be, for example, an area pad, a peripheral pad, or the like. FIG. 12A is a diagram illustrating a layout pattern of an area pad in which electrode pads 1201 are provided over the entire surface of the semiconductor chip 1101. FIG. 12B is a diagram illustrating a layout pattern of a peripheral pad in which electrode pads 1202 are provided in the edge portions of the semiconductor chip 1101. In many cases, the flip-chip connection pad is formed such that the electrode pads form a uniform pattern on the surface of the semiconductor chip 1101.
FIG. 13 is a cross-sectional view illustrating a conventional bump electrode structure formed on the semiconductor chip 1101 shown in FIGS. 11A, 11B, 12A and 12B. In FIG. 13, a conventional bump electrode 1300 has a structure in which a pad-form wiring metal 1302 is positioned in the uppermost layer portion of a silicon 1301, and a wiring metal 1303 is positioned in the same layer as that of the pad-form wiring metal 1302. A pad connecting metal 1304 is positioned on the pad-form wiring metal 1302. The upper surfaces of the silicon 1301 and the pad connecting metal 1304 are covered by a nitride protective film 1305 mainly formed by a nitride film, and a resin material protective film 1306 made of resin material such as a polyimide so as to protect the pad connecting metal 1304. However, a part of the upper surface of the pad connecting metal 1304 forms an opening 1308 which is not covered by the nitride protective film 1305 and the resin material protective film 1306. The pad connecting metal 1304 contacts the barrier metal 1307 at the opening 1308 and therefore the pad connecting metal 1304 electrically connects to the solder bump 1103 formed on the barrier metal 1307.
In the conventional bump electrode 1300, a portion, of the upper surface of the pad connecting metal 1304, which is not covered by the nitride protective film 1305 and the resin material protective film 1306, that is, the opening 1308 at which the pad connecting metal 1304 contacts the barrier metal 1307, is defined in accordance with a range of the resin material protective film 1306. Further, the resin material protective film 1306 is provided in an under-edge potion 1309 below the barrier metal 1307, so that bump stress concentrated on the under-edge portion 1309 below the barrier metal 1307 can be alleviated. The bump stress applied to the under-edge portion 1309 below the barrier metal 1307 is, for example, a stress which is applied to a barrier metal when the solder bump is formed, and a stress which is applied to the solder bump when the semiconductor chip is mounted on the interposer substrate.
However, the structure of the conventional bump electrode 1300 shown in FIG. 13 causes a problem that malfunction that an electrical short often occurs between the solder bumps of the bump electrodes adjacent to each other when plating, which is a typical technique for forming a solder bump, is performed. FIG. 14 is a diagram illustrating a state where the electrical short occurs between the solder bumps 1103 of the bump electrodes 1300, shown in FIG. 13, adjacent to each other. In FIG. 14, a conductive component α is attached to the resin material protective film 1306, and an electrical short occurs between the solder bumps 1103 adjacent to each other through the barrier metals 1307. This is because the conductive component a is often attached to the resin material protective film 1306 while plating is being performed for forming the solder bump 1103.
Another conventional bump electrode for solving the malfunction of the conventional bump electrode 1300 as described above will be described. FIG. 15 is a cross-sectional view of a conventional bump electrode 1500 for solving the malfunction generated in the conventional bump electrode 1300. In FIG. 15, in the conventional bump electrode 1500, a resin material protective film 1506 is provided on a nitride protective film 1305 such that the resin material protective film 1506 does not contact a barrier metal 1507. Therefore, a portion, of the upper surface of the pad connecting metal 1304, which is not covered by the nitride protective film 1305, that is, an opening 1508 at which the pad connecting metal 1304 contacts the barrier metal 1507 is defined in accordance with a range of the nitride protective film 1305.
In the conventional bump electrode 1500 having the structure described above, when plating, which is a typical technique for forming a solder bump, is performed, the electrical short may not easily occur between the solder bumps of the bump electrodes adjacent to each other. FIG. 16 is a diagram illustrating a state where the conductive component a is attached to the resin material protective films 1506 of the bump electrodes 1500, shown in FIG. 15, adjacent to each other. In FIG. 16, even when the conductive component a is attached to the resin material protective film 1506, the electrical short does not occur between the solder bumps 1103 of the bump electrodes 1500 adjacent to each other because the resin material protective film 1506 does not contact the barrier metal 1507.
The structure of the conventional bump electrode described above is disclosed in, for example, Japanese Laid-Open Patent Publication No. 1-114055 and Japanese Laid-Open Patent Publication No. 2006-19550.
However, the conventional bump electrode 1500 shown in FIG. 15 has a problem described below. FIG. 17 is a diagram illustrating the uppermost layer portion of the silicon 1301 including the pad-form wiring metal 1302 and the wiring metal 1303 in the conventional bump electrode 1500 shown in FIG. 15. The edge (indicated by a dashed line 1507a in FIG. 17) of the barrier metal 1507 is above an area 1700 between the pad-form wiring metal 1302 and the wiring metal 1303. In the conventional bump electrode 1500 shown in FIG. 15, the resin material protective film 1506 is not contained in the under-edge portion 1509 below the barrier metal 1507, and therefore a bump stress concentrated on the under-edge portion 1509 below the barrier metal 1507 is not alleviated, although the bump electrode 1300 shown in FIG. 13 is allowed to alleviate the bump stress.
Therefore, there is a problem that a crack is generated in the nitride protective film 1305 due to the bump stress concentrated on the under-edge portion 1509 below the barrier metal 1507. FIG. 18 is an enlarged view of a portion B1 of the bump electrode 1500 shown in FIG. 15. In FIG. 18, a crack 1800 is generated in the nitride protective film 1305 due to bump stress concentrated on the under-edge portion 1509 below the barrier metal 1507.